Hold circuit

ABSTRACT

A hold circuit has a purpose to provide a hold circuit capable of controlling a hold error of an analog hold in the minimum during transferring. A hold circuit keeps a voltage signal, whose voltage level is compensated by operational amplifiers Amp 1  and Amp 2 , at capacitances C 1  and C 2  by two steps, and holding and transferring of voltage data is performed at the different timing. The accuracy is compensated, as well.

FIELD OF THE INVENTION

The present invention relates to a hold circuit to keep a plural numberof successive input data in time series.

BACKGROUND OF THE INVENTION

For example, in a digital filter, a hold circuit keeps an input data intime series and the data is multiplied by a multiplier and integrationis performed. Data once kept is successively transferred to thefollowing hold circuit and input into another multiplier.

Conventionally, in a digital filter, hold and transferred data aredigital data, and a little level down can be omitted. On the other hand,in computers whose main body is an analog operation, it is necessary totreat an analog data, and hold error can not omitted. However, any holdcircuit considering about transferring of hold of an analog data is notknown.

SUMMARY OF THE INVENTION

The present invention is invented so as to solve the above problems andhas a purpose to provide a hold circuit capable of decreasing a holderror of an analog hold during transferring.

A hold circuit according to the present invention keeps a voltagesignal, whose voltage level is compensated by a operational amplifier,at a capacitance by two steps, and a holding and transferring of voltagedata is performed at the different timing. The accuracy is compensated,as well.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit showing an embodiment of a hold circuit relating tothe present invention.

FIG. 2 is a block showing a filter circuit using the same embodiment asFIG. 1.

FIG. 3 is a circuit showing a multiplication circuit in a filtercircuit.

FIG. 4 is a circuit showing an example of a capacitive coupling.

FIG. 5 is a block diagram showing the second embodiment of a filtercircuit.

FIG. 6 is a circuit diagram showing an adding circuit in the secondembodiment of a filter circuit.

PREFERRED EMBODIMENT OF THE PRESENT INVENTION

Hereinafter an embodiment of a hold circuit according to the presentinvention is described with referring to the attached drawings.

A hold circuit H in FIG. 1 has a pair of operational amplifiers Amp₁ andAmp₂ and a pair of field-effect transistors Tr₁ and Tr₂. An input datad_(in) is input to a non-inverted input of Amp₁. An output of Amp₁ isconnected with a drain of Tr₁. A source of Tr₁ is earthed through acapacitance C₁ and fed back to an inverted inputs of Amp₁. A clock CLK₀is input to a gate and Tr₁ is conductive when CLK₀ is high level. At thetime that Tr₁ is conductive, an output of Amp₁ is controlled in orderthat a voltage equal to d_(in) impresses to C₁, and C1 stores electriccharges in order that a charged voltage becomes d_(in).

A charged voltage of C₁ is connected with a non-inverted input of Amp₂.An output of Amp₂ is connected with a drain of Tr₂ and a source of Tr₂is earthed through a capacitance C₂ and fed back to an inverted input ofAmp₂. In Tr₂, a clock CLK₁ of an inverted phase of CLK₀ is input to agate, and Tr₂ is conductive in an opposite positioned phase of Tr₁. WhenTr₂ is conductive, an output of Amp₂ is controlled in order that avoltage equal to d_(in) is impressed to a charged voltage of C₁. C₂stores an electric charge in order that a charged voltage is equal tod_(in). And d_(out) corresponding d_(in) is output. As a result, d_(in)by a 1 clock timing is kept and holding is surely performed by thepredetermined timing because there is no influence in the followingstage during charging of C₁.

A feed back system using operational amplifiers Amp₁ and Amp₂compensates accuracy of outputs, so that a hold error can be controlledin the minimum.

A hold circuit is used for a filter circuit shown in FIG. 2. Holdcircuits are shown by from H₁₁ to H₁₈ and from H₂₁ to H₂₈ in FIG. 2.

In FIG. 2, a hold circuit has the first summing products circuit MC1 andthe second summing products circuit MC2. The first summing productscircuit MC1 is composed of a plural number of serially connected holdcircuits from H₁₁ to H₁₈ and an output of each hold circuit H_(1k) isinput to a multiplication circuit M_(1k). On the other hand, the secondsumming products circuit MC2 is composed of a plural number of seriallyconnected hold circuits from H₂₁ to H₂₈ and an output of each holdcircuit H_(2k) is input to a multiplication circuit M_(2k).

An input data D_(in) is input to the first summing products circuit andit is transferred to the next hold circuit after it is once kept in eachhold circuit. Then, data in time series of D_(in) is kept in each holdcircuit. This time series data is shown by X(t-k). Beforehand, thepredetermined multipliers from a1 to a8 are input to each multiplicationcircuit from M11 to M18, and a following multiplication for the timeseries data is executed.

    mrcuit. This time series data is shown by X(t-k). Beforehand, the predetermined multipliers from a1 to a8 are input to each multiplication circuit from M11 to M18, and a following multiplication for the time series data is executed.

    m.sub.1k =ak×X(t-k)

m_(1k) is a result of multiplication of a multiplying circuit M_(1k).

Outputs of a multiplication circuit M_(1k) and M₁(k+1) are added by anadding circuit A_(1k), and an adding result is output to the next addingcircuit A₁(k+1). Therefore, an adding circuit A₁₇ calculates a total ofoutputs of all multiplying circuits in the first summing productscircuit. A following formula shows the total. ##EQU1##

To the second summing products circuit, an output A₁₇ or an output H₁₈are input as an input data D_(m) through a switch SW, and it istransferred to the next hold circuit after D_(m) is once kept in eachhold circuit from H₂₁ to H₂₈. Then, data of time series of D_(m) is keptin each hold circuit. This sequential data is shown by Y(t-k).Predetermined multipliers from b₁ to b₈ are input in each multiplyingcircuit from M₂₁ to M₂₈, and the following multiplication for the timeseries data is executed.

    m.sub.2k =b.sub.k ×Y(t-k)

m_(2k) is a multiplied result of a multiplying circuit M_(2k).

Outputs of multiplication circuits M_(k2) and M₂(k+1) are added by anadding circuit A_(2k), and the adding result is output to the nextadding circuit A₂(k-1). Therefore, an adding circuit A₂₇ is a total ofoutputs of all multiplying circuits in the second summing productscircuit. Then the total is shown by the following formula 2. ##EQU2##

And, an output of an adding circuit A₂₁ is input to an adding circuitA₁₇ in the first sunning products MC1 and an output of A₁₇ is a total ofmultiplied result of both MC1 and MC2.

When SW is connected with a side of H₁₈, Dm is X (t-8), then an outputof MC2 is shown by formula 3. ##EQU3## Here, expressing b_(k) =a.sub.(k+8). a total of MC1 and MC2 output from A₁₇ is formula 4. ##EQU4## Then acharacteristics of FIR type filter is obtained.

When SW is connected with a side of A₁₇, then formula 5 is shown.##EQU5## Generally expressing Y(t)=D_(m), and a characteristics of IIRtype is obtained.

As mentioned above, switching only SW on a special circuit, SW realizesa filter of two types filters of FIR and IIR are realized and a filterwith a comparative large stages using all hold circuits andmultiplication circuits are realized in FIR type. That is, high speedfilter with wide usage can be realized.

FIG. 3 shows an embodiment of a multiplication circuit M_(jk), M_(jk),has a pair of operational amplifiers Amp₃ and Amp₄, and a pair offield-effects transistors Tr₃ and Tr₄. An input analog data AX is inputto a non-inverted input of Amp₃. An output of Amp₃ is connected with adrain of Tr₃, and a source of Tr₃ is earthed through capacitances C₃ andC₄. A voltage between C₃ and C₄ is fed back to an inverted input ofAmp₃. Tr₃ is conductive when a digital input B is input to a gate and ishigh level. When Tr₃ is conductive controlling an output of Amp₃ inorder that a voltage equal to AX impresses to C₄, and electric change isstored in order that a charged voltage is Ax in C₄. This time, a sourcevoltage of Tr₃ is Ax{(C₃ -C₄)/C₃ }.

In Amp₄, a non-inverted input is earthed, and its output is connectedwith a source of Tr₄. A drain of Tr₄ is earthed to C₃ and fed back to aninverted input of Amp₄. A digital data inverting B by an inverter INV isinput to a gate of Tr₄, and Tr₄ is conductive when B is low level. WhenTr₄ is conductive, an output of Amp₄ is controlled to be 0V at a drainof Tr₄.

A source of Tr₃ and a drain of Tr₄ are connected with a capacitance C₅for outputting, and a voltage value multiplied a weight decided by acapacitive coupling with C₅ is an output. That is,

M_(jk) performs {(C₃ -C₄)/C₃ } C_(cp).

c_(cp) is a weight decided by capacitive coupling. Multiplication bymultiplier 0 is executed.

A capacitive coupling is a circuit as shown in FIG. 4, and consists of aplural number of capacitances parallelly connected (here 8 capacitancesfrom C₅₁ to C₅₈). When voltages from V₁ to V₈ are impressed to thesecapacitances, an output voltage V₈ is shown by a following formula and aweighted addition is executed.

Providing circuits as FIG. 3 parallelly, inputting each bit of a digitaldata as B to the circuit, and setting {(C3-C4)/C3} Ccp in 2^(n), amultiplication of an analog data AX and a digital data is directlyexecuted.

The above adding circuit A_(jk) can be realized by the circuit of FIG. 4with 2 or 3 inputs.

An output signal D_(out) output by above composition is kept once inH_(out).

FIG. 5 shows the second embodiment of a filter circuit. Instead of anadding circuit A_(jk), one adding circuit At is used. If an output ofeach multiplying circuit M_(jk) is m_(jk), then a weighted addition isexecuted by a capacitive coupling of capacitance C_(jk) parallellyconnecting, as shown FIG. 6. The manners of calculation is same as thatof circuit in FIG. 4.

As mentioned above, a hold circuit relating to the present inventionkeeps a voltage signal, whose voltage level is compensated by aoperational amplifier, at a capacitance by two steps, and holding andtransferring of voltage data is performed at the different timing. Theaccuracy is compensated, as well so that a hold circuit capable ofcontrolling a hold error of an analog hold in the minimum duringtransferring.

What is claimed is:
 1. A hold circuit comprising:i) a first operationalamplifier connected with an input data at a non-inverted input; ii) asecond operational amplifier; iii) a first field-effect transistorconnected with an output of said first operational amplifier at a drain;iv) a first capacitance connected at a first terminal with a source ofsaid first field-effect transistor, with an inverted input of said firstoperational amplifier, and with a non-inverted input of said secondoperational amplifier, and connected at a second terminal with theearth; v) a second field-effect transistor connected with an output ofsaid second operational amplifier at a drain; and vi) a secondcapacitance connected at a first terminal with a source of said secondfield-effect transistor and an inverted input of said second operationalamplifier and connected at a second terminal with the earth.